摘要 :
The fabrication of peripheral CMOS devices for DRAM memories requires specific optimization with respect to a standard logic flow, imposed by the additional constraints linked to the memory element fabrication. Several process tun...
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The fabrication of peripheral CMOS devices for DRAM memories requires specific optimization with respect to a standard logic flow, imposed by the additional constraints linked to the memory element fabrication. Several process tunings are needed to keep pace with the request for low leakage and low cost devices combined with the needs of highly performant and resilient circuits. In this article, we summarize the most significant developments achieved in recent years focusing on HKMG Gate stack, junction tuning, silicide optimization for DRAM peripheral transistors. Three different solutions with different fabrication complexity and performance for HKMG, optimized junction, and thermally stable NiPt silicide fabrication, all compatible with the DRAM requirements, are discussed.
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摘要 :
In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k ...
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In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices. In this presentation, gate stack technology using high-k gate dielectrics and metal gate will be discussed, and recent achievements of these technologies will be reviewed.
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摘要 :
In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k ...
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In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices. In this presentation, gate stack technology using high-k gate dielectrics and metal gate will be discussed, and recent achievements of these technologies will be reviewed.
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摘要 :
Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd_2O_3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these...
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Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd_2O_3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd_2O_3 and TiN gate electrodes are presented.
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摘要 :
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (V_(th),) characteri...
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As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (V_(th),) characteristics of the High-k/Metal Gate MOSFET fabricated with 65 nm CMOS process on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (V_(th)-inv) of CMOS inverter is reported in this paper.
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摘要 :
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristic...
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As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristics of the High-k/Metal Gate MOSFET on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (Vth-inv) of CMOS inverter is reported in this paper.
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摘要 :
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristic...
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As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristics of the High-k/Metal Gate MOSFET on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (Vth-inv) of CMOS inverter is reported in this paper.
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摘要 :
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristic...
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As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristics of the High-k/Metal Gate MOSFET on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (Vth-inv) of CMOS inverter is reported in this paper.
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摘要 :
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristic...
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As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristics of the High-k/Metal Gate MOSFET on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (Vth-inv) of CMOS inverter is reported in this paper.
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摘要 :
The optimizations to metal gate structure and film process were extensively investigated for great metal-gate stress (MGS) in 20 nm high-k/metal-gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies...
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The optimizations to metal gate structure and film process were extensively investigated for great metal-gate stress (MGS) in 20 nm high-k/metal-gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values (0 to -6 GPa) was implemented in the device simulation along with other traditional process-induced-strain (PIS) technologies like e-SiC and nitride capping layer. The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down. In addition, the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated. Also with a new method of fully stressed replacement metal gate (FSRMG) and using plane-shape-HfO to substitute U-shape-HfO, the effect of MGS was improved. For greater film stress in the metal gate, the process conditions for physical vapor deposition (PVD) TiN _x were optimized. The maximum compressive stress of -6.5 GPa TiN _x was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.
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